A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.
Samudrala, Praveen K.; Katkoori, Srinivas; and Ramos, Jeremy, "Method and apparatus for creating circuit redundancy in programmable logic devices" (2005). USF Patents. 720.
University of South Florida Honeywell Space Systems, Inc.