Document Type
Patent
Publication Date
August 2007
Patent Number
7256608
Abstract
An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.
Application Number
11/422,973
Recommended Citation
Ranganathan, Nagarajan and Hanchate, Narender, "Method and apparatus for reducing leakage in integrated circuits" (2007). USF Patents. 633.
https://digitalcommons.usf.edu/usf_patents/633
Assignees
University of South Florida
Filing Date
06/08/2006
Primary/U.S. Class
326/26
