Graduation Year
2018
Document Type
Thesis
Degree
M.S.C.S.
Degree Name
MS in Computer Science (M.S.C.S.)
Degree Granting Department
Engineering Computer Science
Major Professor
Srinivas Katkoori, Ph.D.
Committee Member
Robert Karam, Ph.D.
Committee Member
Hao Zheng, Ph.D.
Keywords
Hardware Security, Logic Simulation, Trojan Trigger, Very-Large-Scale-Integration
Abstract
Today multi-million gate integrated circuits are being commonly used in many critical (eg., health care) and sensitive (eg., military) applications. Therefore, they are susceptible to malicious modifications, namely, Hardware Trojans (HTs), with the intent of leaking sensitive information, denial-of-service etc. There are many ways of inserting Hardware Trojans in ICs. Thus, HT detection and mitigation are very important tasks. In this thesis, we propose a novel probabilistic simulation based approach to estimate the susceptibility of a combinational circuit to a HT. One of the common ways is to simulate the netlist with typical input sequences and identifying low activity nets in the design that could be exploited for Hardware Trojans. This approach has the drawback of excessive simulation time. Probabilistic simulation is very efficient as the input sequences are condensed into probabilistic waveforms which are then propagated through the netlist to identify low activity nets. The main advantage of the proposed technique is rapid analysis of a netlist for HT susceptibility. We experimented with eleven MCNC benchmarks and demonstrate significant speedup (approximately 2 x (10^3) to 5 x (10^3) over traditional simulation based approach.
Scholar Commons Citation
Gurram, Venkata Lakshmi Bhargavi, "Gate Level Probabilistic Simulation Based Hardware Trojan Susceptibility Analysis of Combinational Circuits" (2018). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/8117
