Graduation Year
2019
Document Type
Thesis
Degree
M.S.
Degree Name
Master of Science (M.S.)
Degree Granting Department
Computer Science and Engineering
Major Professor
Srinivas Katkoori, Ph.D.
Committee Member
Sriram Chellappan, Ph.D.
Committee Member
Robert Karam, Ph.D.
Keywords
Intellectual Property, Overhead, Resilience, Reverse Engineer, Trojan Horse
Abstract
Intellectual Property (IP) based Integrated Circuit (IC) design is an established approach for the design of a complex System-on-Chip (SoC). Porting the preparatory designs to third-party without enough security margin exposes an attacker to perform reverse engineering (RE) on the designs and hence counterfeiting, IP theft etc., are common now-a-days. Design obfuscation can reduce RE attempt by an attacker. In this work, we propose a key based obfuscation and anonymization method for a behavioral IP. Given a behavioral VHDL description, the assignment and conditional statements are modified by incorporating random boolean operations with unique random key bits. The obfuscated VHDL is then anonymized by random identifiers. The resultant behavioral model can be simulated correctly upon application of original key sequence. Simulation results with nine datapath intensive benchmarks with three different lengths of test sequences show that the simulation overhead is negligible (only a few seconds). We evaluate the probability of reverse engineering the obfuscated design and show that it is extremely low.
Scholar Commons Citation
Kandikonda, Balausha Varshini, "A Key Based Obfuscation and Anonymization of Behavior VHDL Models" (2018). USF Tampa Graduate Theses and Dissertations.
https://digitalcommons.usf.edu/etd/7686
