Degree Granting Department
Computer Science and Engineering
asic, fabrication, fpga, security, trust
Hardware Trojan Horses (HTHs or Trojans) are malicious design modifications intended to cause the design to function incorrectly. Globalization of the IC development industry has created new opportunities for rogue agents to compromise a design in such a way. Offshore foundries cannot always be trusted, and the use of trusted foundries is not always practical or economical. There is a pressing need for a method to reliably detect these Trojans, to prevent compromised designs from being put into production.
This thesis proposes a multi-parameter analysis method that is capable of reliably detecting function-altering and performance-degrading Trojans in FPGA bitstreams. It is largely autonomous, able to perform functional verification and power analysis of a design with minimal user interaction. On-the-fly test vector generation and verification reduces the overhead of test creation by removing the need to pre-generate and verify test vector sets.
We implemented the method on a testbed constructed from COTS components, and tested it using a red-team/blue-team approach. The system was effective at detecting performance-degrading and function-altering embedded within combinational or sequential designs. The method was submitted for consideration in the 2012 Embedded Systems Challenge, which served to independently verify our results and evaluate the method; it was awarded first place in the competition.
Scholar Commons Citation
Bell, Christopher William, "A Multi-Parameter Functional Side Channel Analysis Method for Hardware Trojan Detection in Untrusted FPGA Bitstreams" (2013). Graduate Theses and Dissertations.