Graduation Year
2005
Document Type
Thesis
Degree
M.S.Cp.E.
Degree Granting Department
Computer Engineering
Major Professor
Dr. Srinivas Katkoori.
Keywords
Mtcmos, Speedup, Simulated annealing, Clique-partitioning, Data initiation intervals
Abstract
Traditional approaches for power optimization during high level synthesis, have targetted single-cycle designs where only one input is being processed by the datapath at any given time. Throughput of large single-cycle designs can be improved by means of pipelining. In this work, we present a framework for the high-level synthesis of pipelined datapaths with low leakage power dissipation. We explore the effect of pipelining on the leakage power dissipation of data-flow intensive designs. An algorithm for minimization of leakage power during behavioral pipelining is presented. The transistor level leakage reduction technique employed here is based on Multi-Threshold CMOS (MTCMOS) technology. Pipelined allocation of functional units and registers is performed considering fixed data introduction intervals. Our algorithm uses simulated annealing to perform scheduling, allocation, and binding for obtaining pipelined datapaths that have low leakage dissipation.
Scholar Commons Citation
Gopalan, Ranganath, "Leakage power driven behavioral synthesis of pipelined asics" (2005). Graduate Theses and Dissertations.
https://scholarcommons.usf.edu/etd/2903