Degree Granting Department
gate level, Bayesian network, simulation, sampling, entropy
Power dissipation in a VLSI circuit poses a serious challenge in present and future VLSI design. A switching model for the data dependent behavior of the transistors is essential to model dynamic, load-dependent active power and also leakage power in active mode - the two components of power in a VLSI circuit. A probabilistic Bayesian Network based switching model can explicitly model all spatio-temporal dependency relationships in a combinational circuit, resulting in zero-error estimates. However, the space-time requirements of exact estimation schemes, based on this model, increase with circuit complexity [5, 24]. This work explores a non-simulative, importance sampling based, probabilistic estimation strategy that scales well with circuit complexity. It has the any-time aspect of simulation and the input pattern independence of probabilistic models.
Experimental results with ISCAS'85 benchmark shows a significant savings in time (nearly 3 times) and significant reduction in maximum error (nearly 6 times) especially for large benchmark circuits compared to the existing state of the art technique (Approximate Cascaded Bayesian Network) which is partition based. We also present a novel probabilistic method that is not dependent on the pre-specification of input-statistics or the availability of input-traces, to identify nodes that are likely to be leaky even in the active zone. This work emphasizes on stochastic data dependency and characterization of the input space, targeting data-dependent leakage power. The central theme of this work lies in obtaining the posterior input data distribution, conditioned on the leakage at an individual signal.
We propose a minimal, causal, graphical probabilistic model (Bayesian Belief Network) for computing the posterior, based on probabilistic propagation flow against the causal direction, i.e. towards the input. We also provide two entropy-based measures to characterize the amount of uncertainties in the posterior input space as an indicator of the likelihood of the leakage of a signal. Results on ISCAS'85 benchmark shows that conclusive judgments can be made on many nodes without any prior knowledge about the input space.
Scholar Commons Citation
Ramani, Shiva Shankar, "Graphical probabilistic switching model: Inference and characterization for power dissipation in VLSI circuits" (2004). Graduate Theses and Dissertations.