Degree Granting Department
Computer Science and Engineering
Srinivas Katkoori, Ph.D.
Nagarajan Ranganathan, Ph.D.
Hao Zheng, Ph.D.
Wilfrido Moreno, Ph.D.
A. N. V. Rao, Ph.D.
word-level statistics, probability, floorplanner, routing, synthesis
Downscaling of technology causes signal integrity problems due to crosstalk between closely-spaced interconnect lines. Existing crosstalk estimation and optimization techniques operate at the layout-level of circuits and fail to utilize the efficient design-space exploration at the high-level. To address this, we propose word-level statistical techniques which estimate crosstalk between bus lines: (1) Given a data stream, the first technique simply counts the number of crosstalk events on each bus line. The drawback of this technique is that the execution time is proportional to the stream length. This is overcome by the second enumerative technique which is purely statistical in nature. (2) Given word-level statistics, we estimate the bit-level crosstalk probability of bus lines. (3) We further speedup the statistical method using a non-enumerative technique by linearizing its complexity with respect to the bus width. Average errors of less than 15% are obtained for bus-widths ranging from 8b to 32b while execution times are reduced by two orders of magnitude, compared to HSPICE.
We then measure the crosstalk susceptibility of nets in the post global routing phase (performed using CADENCE Silicon Ensemble), prior to detailed routing using (1) Pt , the probability of crosstalk on victims in different regions along their route; and (2) Vpeak, the maximum crosstalk noise amplitude experienced by victims along their route. Pt is estimated using the fast and accurate statistical estimator we previously proposed. Vpeak is estimated by predicting the cross-coupling capacitances between neighboring wires, using their global routing information. Average errors are less than 8%, compared to HSPICE. We combine the crosstalk susceptibility values from individual regions along a victim wire’s route, to obtain a single susceptibility value for the entire wire.
Further, we propose a register binding technique during high-level synthesis to minimize crosstalk at the register outputs in the RT-level design. It involves modification of the cliquepartitioning algorithm to make crosstalk-aware choices of edges to be mapped to the same register. RT-level comparisons between the regular and crosstalk-aware designs show upto 16% reduction in crosstalk activity at the register outputs.
Scholar Commons Citation
Gupta, Suvodeep, "Behavioral and RT-Level Estimation and Optimization of Crosstalk in VLSI ASICs" (2004). Graduate Theses and Dissertations.