Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
fault detection, cryptography, electrical fault detection, computer architecture, costs, polynomials, hardware, table lookup, error analysis, delay effects
Digital Object Identifier (DOI)
In this paper, the authors present parity-based fault detection architecture of the S-box for designing high performance fault detection structures of the advanced encryption standard. Instead of using look-up tables for the S-box and its parity prediction, logical gate implementations based on the composite field are utilized. After analyzing the error propagation for injected single faults, the authors modify the original S-box and suggest fault detection architecture for the S-box. Using the closed formulations for the predicted parity bits, the authors propose a parity-based fault detection scheme for reaching the maximum fault coverage. Moreover, the overhead costs, including space complexity and time delay of our modified S-box and the parity predictions are also compared to those of the previously reported ones.
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Citation / Publisher Attribution
2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p. 572-580
Scholar Commons Citation
Mozaffari Kermani, Mehran and Reyhani-Masoleh, Arash, "Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard" (2006). Computer Science and Engineering Faculty Publications. 58.