Degree Granting Department
3D integrated chips, 3d via, PLA, Inter-wafer via, MAGIC layout system, VILIC, MPLA
Increased chip size and reduced feature size has helped following Moores law for long decades. This has an impact on interconnect length, which is resulting in chip performance degradation. Despite the introduction of new materials with Low-K dielectrics for interconnects, their delay is expected to substantially limit the chip performance. To overcome this problem the need for new technology has arrived. One such promising technology is the three-dimensional Integrated chips (3D ICs) with multiple silicon layers. In this thesis, three dimensional integrated chip (3D IC) technology has been implemented on programmable logic arrays (PLAs). The two-dimensional PLAs are converted to three-dimensional PLAs to realize the advantages of the third dimension. Two novel approaches for partitioning of PLAs are introduced for topological optimization.
Scholar Commons Citation
Sunki, Supriya, "Performance optimization in three-dimensional programmable logic arrays (PLAs)" (2005). Graduate Theses and Dissertations.