Graduation Year

2005

Document Type

Thesis

Degree

M.S.Cp.E.

Degree Granting Department

Computer Engineering

Major Professor

Dr. Srinivas Katkoori.

Keywords

Radiation, Hardening, Temporal, Redundant gates, Simulator

Abstract

We present a design technique, called partial evaluation triple modular redundancy for hardening combinational circuits against Single Event Upsets (SEU). The input environment is given in terms of signal probabilities of the lines. This is useful information to determine the redundant gates of the given circuit. The basic ideas of partial redundancy and temporal triple modular redundancy are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. This technique fails in cases when the actual inputs to the circuit are not in accordance to the rounded logic values. In such cases the technique of temporal TMR is used. However, there is some overhead in this process because of the voter circuits and the need to choose the outputs computed by partially evaluated circuit and circuit using temporal TMR.

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