Graduation Year


Document Type




Degree Granting Department

Electrical Engineering

Major Professor

Bhanja, Sanjukta.


inference, sampling, clique, simulation, Behavioral Level, Register Transfer Level, bottom-up, top-down


Power consumption is one of the major bottlenecks in current and future VLSI design. Early microprocessors, which consumed a few tens of watts, are now replaced by millions of transistors and with the introduction of easy-to-design tools to explore at unbelievable minimum dimensions, increase in chip density is increasing at a alarming rate and necessitates faster power estimation methods. Gate level power estimation techniques are highly accurate methods but when time is the main constraint, power has to be estimated a lot higher in the abstraction level. Estimating power at higher levels also saves valuable time and cost involved in redesigning when design specifications are not met. We estimate power at every levels of abstraction for a breadth first design-space exploration.

This work targets a stimulus-free pattern-insensitive RT level hierarchical probabilistic model, called Behavioral Induced Directed Acyclic Graph (BIDAG), that can freely traverse between the RT and logic level and we prove that such a model corresponds to a Bayesian Network to map all the dependencies and can be used to model the joint probability distribution of a set of variables. Each node or variable in this structure represents a gate level Directed Acyclic Graph structure, called the Logic Induced Directed Acyclic Graph (LIDAG). We employ Bayesian networks for the exact representation of underlying probabilistic framework at RT level, capturing the dependence exactly and again use the same probabilistic model for the logic level. Bayesian networks are graphical representations used to concisely represent the uncertain knowledge of the system.

In order to get an posterior belief of a query node or variable, with or without preset nodes or variables called the evidence nodes, we use stochastic inference algorithm, based on importance sampling method, called the Evidence Pre-propagation Importance Sampling (EPIS) which is anytime and scales really well for RT and logic networks. Experimental results indicate that this method of estimation yields high accuracy and is qualitatively superior to macro-models under a wider range of input patterns. The main highlights of this work is that as it is a probabilistic model, it is input pattern independent and nonsimulative property implies less time for power modelling.