Degree Granting Department
Computer Science and Engineering
word-level statistics, probability, floorplanner, routing, synthesis
Signal integrity is a very critical parameter in modern digital circuits. The downscaling of technologies to enable miniaturization results in loss of signal integrity on account of crosstalk between interconnect signal lines placed very close to one another. There arises an acute need of methodologies to estimate crosstalk in interconnects and minimize it, in order to generate reliable designs. Although there exist several crosstalk estimation and optimization techniques in literature, most of these techniques operate at the layout-level of circuits. There is a dearth of techniques which tackle the crosstalk estimation and optimization problem at the behavioral and RT-levels where the design-space can be explored more efficiently, compared to the layout-level. We try to fill this void by proposing word-level statistical techniques which estimate crosstalk between different bus lines.
We then integrate the high-level estimators with a place and route tool to estimate crosstalk between different buses at the layout level of designs. Further, we propose a register binding technique during high-level synthesis to minimize register crosstalk activity in the RT-level designs. Specifics related to each proposed technique are presented below. We address the intra-bus crosstalk estimation problem by presenting two high-level techniques to estimate the probability of crosstalk within the lines of a system bus: (1) Given an input data stream, the first technique simply estimates the number of crosstalk events on each line of the bus. The main drawback of this technique is that the execution time is proportional to the stream length. This is overcome by the second enumerative technique which is purely statistical in nature.
(2) Given the word-level statistical parameters, namely mean, standard deviation, and lag-one temporal correlation coefficient, we estimate the bit-level crosstalk probability. Experimental results for data streams from different data environments, compared against detailed HSPICE simulations, are presented. There is an exact match between (1) and the corresponding HSPICE simulations while (2) has less than 7% average error, compared to HSPICE. The estimation time of (2) is significantly less than (1) as well as the HSPICE simulations. However, this enumerative technique still suffers from exponential complexity with respect to the bus-width. In order to speedup the statistical enumerative method, we then propose a statistical non-enumerative technique that has linear time complexity with respect to the bus-width.
We achieve the linear complexity by resorting to: (1) manipulation of the data stream to make the crosstalk-producing values continuous; and (2) sampling the distribution function and storing it as a lookup table. Experimental results for data streams from different data environments are presented, compared against the stream-based approach. Average errors of less than 15% are obtained for bus-widths ranging from 8b to 32b. The estimation time is reduced by over two orders of magnitude, compared to HSPICE. The statistical approaches are shown to be compatible with existing bus re-ordering techniques. Thus, we are able to estimate the crosstalk susceptibility of lines within a bus very efficiently. We then address the problem of estimating crosstalk between different buses at the layout-level of designs. We propose a technique to measure the crosstalk susceptibility of different nets in the post global routing phase, prior to detailed routing of designs.
Global routing provides the approximate routes of the wires. This is used to compute the aggressors of a given victim wire along its route and its crosstalk susceptibility with respect to those aggressors. The crosstalk susceptibility of a wire is given by (1) P(t), the probability of crosstalk occurrence on the wire in different regions along its route; and (2) V(peak), the worst case crosstalk noise amplitude experienced by the wire along its route. P(t) is estimated using the fast and accurate statistical estimator we previously proposed. V(peak) is estimated by predicting the cross-coupling capacitances between neighboring wires, using their global routing information. Placement and global routing are done using CADENCE Silicon Ensemble. The predicted crosstalk estimates are compared against detailed HSPICE simulations. Average errors are found to be less than 8%.
We modify the estimation technique, using a root mean square cost function, to obtain single values for the crosstalk probability and noise amplitude of a victim wire along its entire route by combining the values from individual regions through which it passes. Further, we propose a register binding technique during high-level synthesis to minimize crosstalk at the register outputs in the RT-level design. The technique involves modification of the clique-partitioning algorithm to make crosstalk-aware choices of edges to be mapped to the same register. RT-level comparisons between the regular and crosstalk-aware designs show upto 16% reduction in crosstalk activity at the register outputs.
Scholar Commons Citation
Gupta, Suvodeep, "Behavioral and RT-level estimation and optimization of crosstalk in VLSI ASICs" (2004). Graduate Theses and Dissertations.