Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA
Document Type
Article
Publication Date
1-2017
Keywords
trellis, Error detection, look-ahead technique, recomputing with encoded operands
Digital Object Identifier (DOI)
https://doi.org/10.1109/TCSI.2016.2610187
Abstract
The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-latency, low-complexity Viterbi decoders are presented. The merit of the proposed schemes is that reliability requirements, overhead tolerance, and performance degradation limits are embedded in the structures and can be adapted accordingly. We also present three variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, coupled with signature-based schemes. The instrumented decoder architecture has been subjected to extensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [32 nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-6 family] implementations for benchmark. The proposed fine-grained approaches can be utilized based on reliability objectives and performance/implementation metrics degradation tolerance.
Was this content written or created while at USF?
No
Citation / Publisher Attribution
IEEE Transactions on Circuits and Systems I: Regular Papers, v. 64, issue 1, p. 208-216
Scholar Commons Citation
Mozaffari Kermani, Mehran; Singh, Vineeta; and Azarderakhsh, Reza, "Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA" (2017). Computer Science and Engineering Faculty Publications. 26.
https://digitalcommons.usf.edu/esb_facpub/26
